Calnex is a successful, innovative, electronics company that addresses test and measurement market opportunities in expanding global telecommunications networks.
We develop leading edge T&M products that are used to verify the performance of network equipment and the network itself. We have a particular focus on high accuracy timing testing and network emulation and are recognised globally as experts in these areas. Our products are based on proprietary programmable hardware platforms with software configurable personalities and off instrument analysis packages.
We have an exciting opportunity for a VHDL Design Engineer (Contractor) to join our expanding R&D team. In this role you will develop highly performant VHDL targeting the latest FGPA architectures. You will work as part of our multi-discipline product design teams to deliver new products and enhancements to our existing market leading portfolio.
The successful candidate will be experienced and able to innovate and deliver in a fast paced and busy environment, and enjoy working on leading edge digital designs.
- Creating new high speed FPGA based digital designs and/or modifying existing designs to support delivery of new product features as per specification.
- Estimating timescales based on an outline of the requirements and then delivering to those timescales.
- Support quality oriented activities to deliver a product that will delight our customers.
- Learn the domain and hence appreciate the real life use cases of our product features.
Essential Skills, Experience and Qualifications:
- Educated to Degree level in Electronics or equivalent subject
- Proven VHDL experience on high speed designs with complex clocking architectures
- Ability to define digital architectures from a product specification
- Ability to work closely with others in a multi-discipline team
- Detail orientated and driven to deliver in dynamic environment
Experience in any of the following specific areas will also be beneficial:
- Large, complex designs on Xilinx Ultrascale and/or Ultrascale+ series using Vivado & ModelSim
- Matching execution times and path delays
- Board level schematic design incorporating Microprocessor, DDR, QDR SRAM/SDRAM.
- Knowledge of Ethernet packet structures and Telecoms Framing structures.
Off-payroll working rules (IR35) do not apply.
In consideration of the General Data Protection Regulation (GDPR), please be aware that by applying for a role in Calnex Solutions directly or via an intermediary you are giving permission for us to retain certain personal information for a period of up to two years. That information includes your CV, cover letter or any other correspondence relating to your application and any notes we may take at interview.